That’s… debatable. While the R in ARM does stand for RISC, there are way too many instructions in the base instruction set of the latest ARM ISA for me to comfortably call it a RISC architecture, especially when compared to RISC-V, which has an extremely slim base instruction set comparatively.
https://arm.jonpalmisc.com/latest_aarch64/index.html (Just the base instruction set for the latest ARM architecture without any extensions)
https://en.wikipedia.org/wiki/RISC-V_instruction_listings (Look at just the I instructions for the base instruction set without the extensions)
That’s… debatable. While the R in ARM does stand for RISC, there are way too many instructions in the base instruction set of the latest ARM ISA for me to comfortably call it a RISC architecture, especially when compared to RISC-V, which has an extremely slim base instruction set comparatively.