Not really. Unlike x86, an ARM implementation doesn’t have to be compatible to any of the existing CPUs. That’s because of its nature being RISC it can be adapted and changed. There is no core ARM set that has to be implemented by every ARM CPU like x86 does, so that base compatibility is guaranteed. Just because a few CPUs in the family were compatible, doesn’t make the entire architecture design well defined… it cannot be by nature being a RISC implementation.
Not really. Unlike x86, an ARM implementation doesn’t have to be compatible to any of the existing CPUs. That’s because of its nature being RISC it can be adapted and changed. There is no core ARM set that has to be implemented by every ARM CPU like x86 does, so that base compatibility is guaranteed. Just because a few CPUs in the family were compatible, doesn’t make the entire architecture design well defined… it cannot be by nature being a RISC implementation.
This statement is just fundamentally wrong. And it looks like someone else explained this better than I did.
But there is. There is a base ISA. It looks like you have several fundamental misunderstandings…